The present invention relates to a semiconductor device and a method for fabricating the same, more particularly, to a Schottky barrier tunnel transistor and a method for fabricating the same.
Advancement in semiconductor technology and equipment leads to fabrication of transistors with a short channel of 100 nanometers (nm) or less. Devices following the typical simple electrical physical laws accompany quantum mechanical phenomena. A single electron transistor (SET) is one representative example for such devices.
A conventional structure of the SET usually uses a barrier that is generated by forming a pattern in an artificial shape over a silicon-based structure using a difference in an oxidation rate relying on a pattern. This characteristic may worsen an operational characteristic of a device in view of the Moore's law.
In a transistor with a channel length less than 100 nm, leakage current is likely to occur due to a short channel effect. Thus, an appropriate control is generally required. In an attempt to suppress the short channel effect, the junction depth of a source and a drain needs to be in a range of ⅓ to ¼ of the channel length. Although many researchers put an effect to form a shallow junction with low accelerating voltage while continuously using an ion implantation, implemented typically in semiconductor fabrication processes, it is often difficult to control the junction depth of the source and the drain to be shallow and uniform below 30 nm. Thus, one suggested method is to diffuse impurity ions using a rapid thermal process (RTP), a laser annealing process, or a solid phase diffusion (SPD) process. However, this impurity ion diffusion method may be limited to obtain a junction depth of 10 nm or less. Furthermore, as the junction depth decreases, parasitic resistance components of the source and drain including a source-drain extension region caused by the diffusion of the impurity ions increase. Based on this relationship, in the assumption that a doping concentration is 1×1019 atoms/cm3 and a junction depth is 10 nm, a sheet resistance is 500 ohms (Ω)/sq. or more. This value exceeds a sheet resistance of about 300 (Ω)/sq. proposed by the international technology roadmap for semiconductor (ITRS), and may cause a limitation such as signal delay.
In addition to the implementation of the shallow junction depth of the source and drain, permittivity of a gate insulation layer (e.g., oxide) needs to increase to suppress the short channel effect. Many researches have been done to replace a silicon oxide layer, which is typically used in these days, with an oxide layer containing a rare earth metal of a high dielectric constant. However, as compared with the silicon oxide layer, the rare earth metal-based oxide layer may not be effectively heat treated due to its thermal instability. Therefore, a heat treatment in semiconductor processes needs to be performed at low temperature to use such a rare earth metal-based oxide layer. In that case, a heat treatment that proceeds after the ion implantation to activate ions and recover crystal damage may be performed with some limitations.
For the minimization of metal oxide semiconductor field effect transistors (MOSFETs), those limitations associated with a gate oxide material and shallow junctions between source-drain regions and channels need to be overcome in respect of the short channel effect. One proposed approach is Schottky barrier tunnel transistor (SBTT) technology. In detail, source and drain regions of MOSFETs are replaced with a metal or silicide. As compared with the conventional MOSFETs, the sheet resistance measured when the SBTT technology is employed decreases by 1/10-fold to 1/50-fold. Thus, an operation speed can be improved, and a channel length can decrease to 35 nm or less. Also, since an ion implantation is not necessary, a subsequent heat treatment is also not necessary. As a result, a process for fabricating devices using a gate oxide layer based on a high-K dielectric material can be co-used in the SBTT technology. As compared with the conventional MOSFET technology, even though the subsequent heat treatment is implemented, the heat treatment is performed at low temperature. Thus, a process of forming gates based on a metal can be co-used in the SBTT technology.
FIG. 1 illustrates a cross-sectional view of a conventional SBTT structure. The SBTT includes: a substrate 10; a buried oxide layer 11 formed on the substrate 10; source and drain regions 12 formed inside a silicon-on-insulator (SOI) substrate, which is formed on the buried oxide layer 11; a gate insulation layer 13 formed on a channel region 16 of the SOI substrate; a gate electrode 14 formed on the gate insulation layer 13; and spacers 15 formed on both sidewalls of the gate electrode 14.
The conventional SBTT is formed to have a vertical structure in which the gate insulation layer 13 and the gate electrode 14 are formed in sequence on the SOI substrate. The conventional SBTT structure is similar to the conventional MOSFET structure. Different from the conventional MOSFET fabrication process, the source and drain regions 12 in the SBTT structure are not formed by the ion implantation but usually by a sputtering method. Based on the sputtering method, a thin metal film is first deposited, and heat treated to form a silicide layer.
However, since the conventional SBTT has a structure in which the gate insulation layer is interposed underneath the gate electrode, in consideration of the short channel effect, the gate insulation layer may be formed of a high-K dielectric material-based thin film, or the thickness of the gate insulate layer needs to be reduced. In the case of using polysilicon as a gate electrode material, an effective oxide thickness increases due to a depletion effect observed between the gate electrode and the gate insulation layer. In particular, the conventional SBTT technology may have a difficulty in satisfying a required effective oxide thickness of 1.5 nm or less in a device with a line width of 50 nm or less. Also, among high-K dielectric thin films, it may still be difficult to develop a thin film that can have a stable effective insulation thickness of 2 nm or less.